Yasuo Ishii, Mary Inaba, Kei Hiraki.
High Performance, Energy Efficient and Scalable Memory Subsystem Design for Many Core Processors
.in the International Symposium on Computics: Quantum Simulation and Design (ISC-QSD).Toyonaka, Osaka, Japan.October2012.--Articles snd ConferencesYasuo Ishii, Mary Inaba, Kei Hiraki.
Unified Memory Optimizing Architecture: Memory Subsystem Control with a Unified Predictor
.in the 26th International Conference on Supercomputing.Venice, Italy.June2012.--Articles snd ConferencesTomohiro Sonobe, Mary Inaba.
Counter Implication Restart for Parallel SAT Solvers
.in the Learning and Intelligent Optimization Conference, LION6.Paris, France.January2012.--Articles snd ConferencesYasuo Ishii, Takeo Sawada, Keisuke Kuroyanagi, Mary Inaba, Kei Hiraki.
Bimode Cascading: Adaptive Rehashing for ITTAGE Indirect Branch Predictor
.in the 2nd JILP Workshop on Computer Architecture Competitions (JWAC-2): Championship Branch Prediction.San Jose, CA, USA.June2011.--Articles snd ConferencesYasuo Ishii, Keisuke Kuroyanagi, Takeo Sawada, Mary Inaba, Kei Hiraki.
Revisiting Local History for Improving Fused Two-Level Branch Predictor
.in the 2nd JILP Workshop on Computer Architecture Competitions (JWAC-2): Championship Branch Prediction.San Jose, CA, USA.June2011.--Articles snd Conferences